1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to output drivers that prevent degradation of the performance of a channel bus line in a memory module when multiple semiconductor memory devices are connected to the channel bus line.
2. Description of the Related Art
The performance of a memory device generally depends on the input/output data rate, namely, the bandwidth of the memory device. The bandwidth can be increased by increasing the number of parallel input/output data bits or by increasing the access speed or rate. Extended data output dynamic random access memories (EDO DRAMs) and synchronous DRAMs (SDRAMs) are representative memory devices that include a large number of parallel input/output data bits to provide a high bandwidth. Rambus DRAMs (RDRAMs) are representative memory devices that use fast access operations to provide a high bandwidth. For an RDRAM, a data input/output rule such as x16 or x18 defines the number of data (DQ) pins and controls the amount of data simultaneously read from or written to the RDRAM. A typical RDRAM can output two bytes of data in 1.25 ns (i.e., at a rate 800 MHz) and outputs 16 bytes of data in eight cycles. Internally, the RDRAM performs an input/output operation on 128 (x128) or 144 (x144) bits of data at one time at a rate of 100 MHz. Therefore, the RDRAM demultiplexes or combines eight, 16-bit input data values into 128 internal bits of data by way of a serial-to-parallel prefetch during a write operation, and multiplexes 128 internal bits of data into 16-bit output data values by way of a parallel-to-serial prefetch during a read operation.
As shown in FIG. 1, a conventional Rambus module 5 includes a plurality of RDRAMs 11 through 14 sharing the channel bus lines. In particular, the DQ pins (DQA0 through DQA7 and DQB0 through DQB7 of FIG. 1) of each RDRAM connect to channel bus lines C_DQA0 through C_DQA7 and C_DQB0 through C_DQB7 of the Rambus module 5. In the Rambus module 5, a Rambus memory controller (RMC) 10 communicates with RDRAMs 11 through 14 via channel bus lines C_DQA0 through C_DQB7. To achieve a high bandwidth for the Rambus module 5, the channel bus lines C_DQA0 through C_DQB7 must have signal integrity characteristics that satisfy a type of input/output referred to as a Rambus signal level (RSL). To achieve the required RSL, output drivers in the RDRAMs 11 through 14 adjust the value ROL of an output resistance to maintain output current IOL in a proper range and must control or adjust the slew rate of output data according to changes in temperature.
FIG. 2 shows output drivers 21 through 24 of the RDRAMs 11 through 14, which are connected to one channel bus line C_DQA0.
Referring to FIG. 2, the output drivers 21 through 24 respond to output driver enable signals Vgate1 through VgateN and memory data DATA1 through DATAN from DQA0 blocks within the RDRAMs 11 through 14. The RMC 10 of FIG. 1 simultaneously activates the output driver enable signals Vgate1 through VgateN in response to control signals and device IDs. On the other hand, only one memory data (for example, DATA1) from a selected RDRAM (for example, 11) is activated among the memory data DATA1 through DATAN. Thus, when RDRAM 11 is selected, output driver 21 and the memory data DATA1 control the signal level on the channel bus line C_DQA0.
Transistors M11, M21, M31, . . . MN1 turn on in response to activation of the output driver enable signals Vgate1 through VgateN, which are simultaneously activated for the output drivers 21, 22, 23, . . . 24. The simultaneous activation of transistors M11 through MN1 increases the capacitance of the channel bus line C_DQA0. Transmission of data from the selected RDRAM requires charging or discharging of the increased capacitance of the channel bus line C_DQA0. Therefore, the voltage swings for the different data values on the channel bus line C_DQA0 decrease. Moreover, the input logic low/logic high voltage (VIL/VIH) characteristics, the input setup time/input hold time (tSS/tSH) characteristics or the temperature (tQMIN/MAX) characteristics of the channel bus line C_DQA0 are degraded when the number of RDRAMs sharing the channel bus line C_DQA0 increases.
Therefore, an output driver and a memory module are needed that can prevent degradation of a channel bus line even if the number of RDRAMs sharing the channel bus line increases.